Also called: EDA Flow Engineer, Design Methodology Engineer
Builds and maintains the software tool chains chip designers use, so a billion-transistor design can flow from code to the factory without errors.
Designers complain a timing check takes 14 hours, so you profile the script and split the job across 200 servers. You install a new release of the layout software and run test designs to make sure nothing broke. Then you write a guide for the team on a new rule from the chip factory.
Estimated from chip and EDA company postings.
Approximate: anchored on Bureau of Labor Statistics data for a broader job group.
Bachelor's degree (4-year), about 4 years after high school. Bachelor's in electrical or computer engineering; many have a master's in VLSI.
Ways in: 4-year college, Graduate school. Training cost: $15k – $60k.
Majors to look at: Computer Engineering, Electrical Engineering, Computer Science.
Growing faster than average. The US chip-building push and CHIPS Act funding are adding design teams.
Medium risk for 10 years. AI is creeping into chip tools, but keeping complex tool flows correct for real chip launches still needs experts.
Classes: AP Computer Science, AP Physics, AP Calculus.
Official data: O*NET occupation 15-1252.
Career Universe is an early version. Pay, training and AI-risk figures are estimates to start your own research, not verified facts. The research was written with AI research assistants, checked by validation scripts and spot-checked by hand. Check anything important with schools, employers and official sources. How the numbers work.